1. Field of the Invention
The present invention relates generally to an image processing apparatus and method and, more particularly, to an image processing apparatus and method for performing a discrete cosine transform.
2. Description of the Related Art
Discrete cosine transform (DCT) and quantization processes perform lossy compression and have high complexity.
In order to compress an image, DCT converts image data in a spatial domain into DCT coefficients in a frequency domain, and as a result, DCT has the characteristic of decorrelation with energy compaction. DCT is calculated per block, and a converted DCT coefficient is divided into a low frequency region and a high frequency region in the block. A majority of energy components of a signal are concentrated in the low frequency region.
In the spatial domain, correlation between image data is high, while the DCT coefficients in the frequency domain eliminate correlation between coefficients. Accordingly, quantization eliminates signals of the high frequency region which do not significantly affect image quality to allow for the performing of lossy compression by using human visual system (HVS) characteristics.
Generally, a separable transform scheme is applied for a 2-dimensional DCT (2D-DCT) operation. In detail, one dimensional DCT (1D-DCT) is first performed on 8×8 pixel blocks in a row direction, and then another 1D-DCT is performed on the result in a column direction.
As shown in FIG. 1, the DCT operation is divided into a total of six stages, and has multiplication as shown in Table 1 below and fixed constants with respect to scaled DCT coefficients c0 to c7. Here, the computation (or calculation) of the scaled DCT coefficients c0 to c7 may be included in a quantization process in which a division operation is performed after the 2D-DCT in order to reduce computational quantity.
TABLE 10.1250.0901199780.0956708580.1063037620.1250.1590948230.2309698830.4530637230.0901199780.0649728830.0689748450.0766407410.0901199780.1147009750.1665200060.3266407410.0956708580.0689748450.0732233050.0813613770.0956708580.1217659060.1767766950.3467599610.1063037620.0766407410.0813613770.0904039180.1063037620.1352990250.196423740.3852990250.1250.0901199780.0956708580.1063037620.1250.1590948230.2309698830.4530637230.1590948230.1147009750.1217659060.1352990250.1590948230.2024893010.2939689010.5766407410.2309698830.1665200060.1767766950.196423740.2309698830.2939689010.4267766950.8371526020.4530637230.3266407410.3467599610.3852990250.4530637230.5766407410.8371526021.642133898
In order to perform 1D-DCT on eight pixels, five multiplication processes and 29 addition processes must be performed, and in order to perform 2D-DCT on 8×8 pixel blocks, a total of 80 multiplication processes and 464 addition processes must be performed. When the separable transform scheme is employed to implement 2D-DCT with respect to 8×8 pixel blocks, an arithmetic operation unit must perform 10 multiplication processes (5×2=10) and 58 addition (29×2=58) processes.
The related art for 2D-DCT requires a relatively large computational quantity, which, thus, has difficulties in satisfying requirements of a SoC type CMOS image sensor for low complexity and high speed operation.